Voltage converter using mos transistor

ABSTRACT

The invention relates to a voltage converter for generating an output voltage at an output terminal from an input voltage VDD taken from ground GND, said voltage converter comprising a switched capacitance Cp arranged in a bridge of transistors of the MOS type functioning as switches, each transistor being controlled by a control signal having a level varying in the rhythm of a clock signal clock. The invention is characterized in that the converter comprises at least a control circuit for supplying said control signal applied between the gate and the source of one of the transistors functioning as a switch, said control circuit having the particular function of generating a control signal having an amplitude which is inversely proportional to the input voltage VDD when the transistor which it controls is equivalent to a closed switch.

FIELD OF THE INVENTION

The invention relates to a voltage converter for generating an outputvoltage at an output terminal from an input voltage VDD taken fromground GND, said voltage converter comprising:

-   -   a capacitance Cp having a first terminal N1 and a second        terminal N2,    -   four transistors T1-T2-T3-T4 of the MOS type functioning as        switches, each transistor being controlled by a control signal        having a level varying in the rhythm of a clock signal, each        transistor comprising a source, a gate, a drain, and such that        the first transistor T1 is connected between the input voltage        VDD and the first terminal N1, the second transistor T2 is        connected between the first terminal N1 and ground GND, the        third transistor T3 is connected between the input voltage VDD        and the second terminal N2, and the fourth transistor T4 is        connected between the second terminal N2 and the output        terminal.

The invention finds numerous applications in electronic apparatus withvoltage converters using MOS-type transistors.

BACKGROUND OF THE INVENTION

Numerous electronic equipment having only one input voltage of a lowlevel use a voltage converter with which an output voltage of a higheramplitude can be generated. Particularly, voltage doublers are currentlyused for multiplying the amplitude of the input voltage by two.

FIG. 1 shows a prior-art voltage converter referred to as “switchedcapacity” converter. This is a voltage doubler.

This voltage converter uses four transistors T1-T2-T3-T4 functioning asswitches, as well as a capacitance Cp. The transistors T2 and T3 areclosed at the high levels of the clock signal CLK, while the transistorsT1 and T4 are closed at the low levels of the clock signal CLK via theinverter INV.

When T2 and T3 are equivalent to closed switches, the capacitance Cp ischarged until it has a potential difference U_(cp)=VDD at its terminals.When T1 and T4 are, in their turn, equivalent to closed switches, theterminal N1 is connected to the input voltage VDD which, taking thecharge state of the capacitance Cp into account, brings the outputterminal Vout to the potential 2*VDD.

The capacitance Cr does not have an important role for the function ofthe converter but allows a reduction of the ripple of the outputvoltage.

This type of voltage converter has a certain number of limitations whenthe level of the input voltage varies from one electronic apparatus toanother.

At different switching instants of the switches T2-T3 and T1-T4, thecapacitance Cp is charged with a time constant which is defined by theresistances of the drain-source junctions of the transistors T2-T3 andT1-T4. The peaks of the switching current Ic at different switchinginstants are therefore proportional to the input voltage VDD andinversely proportional to the resistance of the drain-source R_(MOS) ofthe transistors T2-T3 and T1-T4. The switching current Ic thus has theform of:Ic=K1.VDD/R _(MOS) with K1=constant  Eq. 1Moreover, when they are equivalent to closed switches, the resistanceR_(MOS) of the transistors T1-T2-T3-T4 of the MOS type is inverselyproportional to their gate-source voltage, i.e. inversely proportionalto the input voltage VDD when they are equivalent to closed switcheswhen a potential difference V_(GS0) of the amplitude VDD is appliedbetween their gate and their source via the signal CLK. The resistanceR_(MOS) of each transistor T1-T2-T3-T4 is thus in the form of:R _(MOS) =K2/V _(GS0) with K2=constant R _(MOS) =K2/VDD  Eq. 2While taking Eq. 1 into account, the switching current Ic increases in aquadratic manner as a function of the input voltage VDD. Consequently,it has the form of:Ic=K3.VDD² with K3=constant  Eq. 3

These switching current peaks generate parasitic noise which is strongeras the amplitude of the peaks is higher. Particularly if the inputvoltage VDD increases from electronic equipment to electronic equipment,the parasitic noise also increases. Taking into account that the currentIc increases in a quadratic manner as a function of the input voltageVDD, a small variation of the input voltage VDD involves a considerablevariation of the switching current and thus of the parasitic noise.

With such a voltage converter, the noise level can therefore not beguaranteed at a constant level when the input voltage VDD varies, evenif VDD varies only very slightly. This technical limitation of such aprior-art converter is particularly annoying for satisfying therequirements of electromagnetic compatibility standards.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide a voltage converter withwhich the variations of the switching current can be reduced.

To this end, the voltage converter is characterized in that it comprisesat least a control circuit for supplying said control signal appliedbetween the gate and the source of one of the transistors T1-T2-T3functioning as a switch, said control circuit having the particularfunction of generating a control signal having an amplitude which isinversely proportional to the input voltage VDD when the transistorwhich it controls is equivalent to a closed switch.

The control signal V_(GS) generated by the control circuit according tothe invention has the form of:V _(GS) =K4/VDD with K2=constant  Eq. 4The resistance R_(MOS) of the transistor controlled by the controlcircuit has the form of:R _(MOS) =K2/V _(GS) with K2=constant  Eq. 5Taking Eq. 4 and Eq. 5 into account, the resistance R_(MOS) will beproportional to the input voltage VDD. The resistance R_(MOS) has theform of:R_(MOS)=K5.VDD with K5=constant  Eq. 6Taking Eq. 1 and Eq. 6 into account, the switching current Ic will beinvariant at the variations of the input voltage VDD. The switchingcurrent thus has the form of:Ic=K6 with K6=constant  Eq. 7

The variations of the peaks of the switching current Ic at differentswitching instants of the transistors T2-T3 and T1-T4 are thus canceledby generating a control signal having an amplitude which is inverselyproportional to the input voltage VDD. The peaks of the switchingcurrent Ic are thus invariant with respect to the variations of theinput voltage VDD, which guarantees a constant noise level when theinput voltage VDD varies.

The invention is also characterized in that said control circuitcomprises, when it controls a transistor of the P-MOS type:

-   -   an additional transistor M1 of the P-MOS type functioning as a        closed switch,    -   a current source IREF_1 arranged in series with the drain-source        junction of said additional transistor M1,    -   a switch COM1 having two inputs, the first input E1 of which is        connected to the central tap P of the additional transistor M1        and the current source IREF_1, and the second input E2 is        connected to the input voltage VDD, said switch being controlled        via said clock signal.

This association of means provides the possibility of generating, at lowcost, a control signal having an amplitude which is inverselyproportional to the input voltage VDD.

An additional advantage of this particular embodiment is the very goodcompensation of the variations of the resistance R_(MOS) of theadditional transistor and the transistor controlled by the controlcircuit in so far as these transistors may be identical.

The invention is also characterized in that said control circuitcomprises, when it controls a transistor of the N-MOS type:

-   -   an additional transistor M2 of the N-MOS type functioning as a        closed switch,    -   a current source IREF_2 arranged in series with the drain-source        junction of said additional transistor M2,    -   a switch COM2 having two inputs, the first input E1 of which is        connected to the central tap P of the additional transistor M2        and the current source IREF_2, and the second input E2 is        connected to ground GND, said switch being controlled via said        clock signal.

This association of means provides the possibility of generating, at lowcost, a control signal having an amplitude which is inverselyproportional to the input voltage VDD.

An additional advantage of this particular embodiment is the very goodcompensation of the variations of the resistance R_(MOS) of theadditional transistor and the transistor controlled by the controlcircuit in so far as these transistors may be identical.

The invention also relates to an integrated circuit, comprising avoltage converter according to the invention.

The invention also relates to a device for reading smart cardscomprising a voltage converter according to the invention for generatingan output voltage having a higher amplitude from an input voltage. Thisoutput voltage is intended to serve as input voltage for a voltageregulator supplying a set of output voltages for feeding a smart card,and thus provides the possibility of exchanging data between the readingdevice and the smart card.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention are apparent from and will beelucidated, by way of non-limitative example, with reference to theembodiment(s) described hereinafter.

In the drawings:

FIG. 1 shows a voltage converter of the prior art,

FIG. 2 shows a voltage converter according to the invention,

FIG. 3 is a first control circuit for controlling transistors of theP-MOS type in a voltage converter according to the invention,

FIG. 4 is a second control circuit for controlling transistors of theN-MOS type in a voltage converter according to the invention,

FIG. 5 shows a device for reading smart cards, comprising a voltageconverter according to the invention.

DESCRIPTION OF EMBODIMENTS

FIG. 2 shows a voltage converter according to the invention. Thisconverter is based on the same operating principle as the prior-artvoltage converter described with reference to FIG. 1.

To this end, the converter shown in FIG. 2 uses transistors T1-T2-T3-T4of the MOS type functioning as switches. The transistors T1-T3-T4 are ofthe P-MOS type while the transistor T2 is of the N-MOS type.

When the transistors T2-T3 are equivalent to closed switches, thetransistors T1-T4 are equivalent to open switches. Inversely, when thetransistors T2-T3 are equivalent to open switches, the transistors T1-T4are equivalent to closed switches. The change of state of thetransistors T1-T2-T3-T4 functioning as switches is effected in therhythm of the clock signal CLK.

The switching cycle of the transistors T1-T2-T3-T4 allows charging ofthe capacitance Cp when the transistors T2-T3 are equivalent to closedswitches so as to supply an output voltage Vout having a level which ishigher than the input voltage VDD when the transistors T1-T4 areequivalent to closed switches.

The transistors T1-T2-T3 are controlled by control circuits according tothe invention so as to allow a change of state of the transistorsT1-T2-T3 functioning as switches by generating a control signal appliedbetween the gate and the source of each transistor controlled in thisway.

The control circuits C1 and C3 are identical because they control bothtransistors of the P-MOS type. The control circuit C1 controlling thetransistor T1 supplies a control signal which varies in the rhythm ofthe inverse value of the clock signal CLK via the inverter INV, whilethe control circuit C3 supplies a control signal which varies in therhythm of the clock signal CLK. The control circuit C2 dedicated to thecontrol of a transistor of the N-MOS type supplies a control signalwhich varies in the rhythm of the clock signal CLK.

Each control circuit is characterized in that it supplies a controlsignal having an amplitude which is inversely proportional to the inputvoltage VDD when the transistor which it controls is equivalent to aclosed switch. This has the result that the resistance R_(MOS) of eachtransistor controlled by the control circuit becomes proportional to theinput voltage VDD. Consequently, the switching current Ic becomesinvariant to the variations of the input voltage VDD.

Each control circuit thus provides the possibility of supplying saidcontrol signal at such a potential level that it enables the transistorwhich it controls to function as an open switch. To this end, thecontrol signal has the level of the input voltage VDD if the controlledtransistor is of the P-MOS type and has the level of ground GND if thecontrolled transistor is of the N-MOS type.

The capacitance Cr does not play a major role as regards the operatingprinciple of the converter, but it allows a reduction of the ripple ofthe output voltage Vout.

The transistor T4 of the P-MOS type is directly controlled at its gateby the clock signal CLK in such a way that it is equivalent to a closedor an open switch at the same time as the transistor T1.

Although FIG. 2 shows a converter using a control circuit for eachtransistor T1, T2 and T3, the invention also provides a voltageconverter (not shown) in which only one or two of the transistors T1, T2and T3 are controlled by a control circuit. This converter provides thepossibility of obtaining a converter at lower cost because the number ofcontrol circuits is reduced.

FIG. 3 is a first control circuit for controlling transistors of theP-MOS type in a voltage converter according to the invention.

Such a control circuit C1 is used for controlling the transistor T1 ofthe P-MOS type, and such a control circuit C3 is used for controllingthe transistor T3 of the P-MOS type.

Each control circuit comprises an additional transistor M1 of the P-MOStype functioning as a closed switch. To this end, the gate of thetransistor M1 is connected to ground GND so that a potential differenceV_(GS0)=VDD is applied between the gate and the source of M1.

The control circuit also comprises a current source IREF_1 arranged inseries with the drain-source junction of said digital transistor M1.This current source supplies a current IREF_1 in the drain-sourcejunction of said additional transistor M1. The value of the currentIREF_1 is constant and is particularly independent of the input voltageVDD.

The control circuit also comprises a switch COM1 having two inputs E1and E2, the first input E1 being connected to the central tap of theadditional transistor and the current source, the second input E2 beingconnected to the input voltage VDD.

The switch COM1 is controlled by the clock signal CLK_IN1. For thecontrol circuit C1, the clock signal CLK_IN1 corresponds to the clocksignal supplied at the output of the inverter INV of FIG. 2. For thecontrol circuit C3, the clock signal CLK_IN1 corresponds to the clocksignal CLK of FIG. 2.

When the clock signal CLK_IN1 is at the low level, i.e. at ground GND, apotential VDD is applied to the gate of transistor T1/T3. The controlcircuit thus applies a potential difference V_(GS)=0 between the gateand the source of the transistor T1/T3. Consequently, the transistorT1/T3 is equivalent to an open switch.

When the clock signal CLK_IN1 is at the high level, i.e. at the inputvoltage VDD, a potential V_(GS) which is equal to that at the centraltap P between the current source IREF_1 and the drain-source junction ofM1 is applied to the gate of the transistor T1/T3. The control circuitthus applies a potential difference V_(GS) between the gate and thesource of the transistor T1/T3, which is equal to the potentialdifference at the terminals of the drain-source junction of thetransistor M1, which potential difference is inversely proportional tothe input voltage VDD. Since the potential at the tap P has a smallvalue, the potential difference V_(GS) has a value which is sufficientlyhigh to render the transistor T1/T3 equivalent to a closed switch.

In other words, when such a control circuit controls a transistor of theP-MOS type equivalent to a closed switch, it provides the possibility ofapplying a potential V_(G) to the gate of the transistor T1/T3 which isslightly higher than ground GND by a quantity ε(of about several volts)so as to get rid of fluctuations of the input voltage VDD, in contrastto the prior-art converter in which a potential which is equal to GNDwould be applied to the gate of the transistor T1/T3.

In a particular embodiment, the inputs E1 and E2 of the switch COM1 ofthe switching circuit C 1 are advantageously inverted in such a way thatthe clock signal CLK_IN1 corresponds to the clock signal CLK, thuseconomizing on the inverter INV.

FIG. 4 shows a second control circuit for controlling transistors of theN-MOS type in a converter according to the invention.

Such a control circuit C2 is used for controlling the transistor T2 ofthe N-MOS type.

The control circuit C2 comprises an additional transistor M2 of theN-MOS type functioning as a closed switch. To this end, the gate of thetransistor M2 is connected to the input voltage VDD so as to apply apotential difference V_(GS0)=VDD between the gate and the source of M2.

The control circuit also comprises a current source IREF_2 arranged inseries with the drain-source junction of said additional transistor M2.This current source supplies a current IREF_2 in the drain-sourcejunction of said additional transistor M2. The value of the currentIREF_2 is constant and is particularly independent of the input voltageVDD.

The control circuit also comprises a switch COM2 having two inputs E1and E2, the first input E1 being connected to the central tap of theadditional transistor and the current source, the second input E2 beingconnected to ground GND.

The switch COM2 is controlled by the clock signal CLK_IN2. The clocksignal CLK_IN2 corresponds to the clock signal CLK of FIG. 2.

When the clock signal CLK_IN2 is at the low level, i.e. at ground GND, apotential GND is applied to the gate of transistor T2. The controlcircuit thus applies a potential difference V_(GS)=0 between the gateand the source of the transistor T2. Consequently, the transistor T2 isequivalent to an open switch.

When the clock signal CLK_IN2 is at the high level, i.e. at the inputvoltage VDD, a potential V_(G) which is equal to that of the central tapP between the current source IREF_2 and the drain-source junction of M2is applied to the gate of the transistor T2. The control circuit thusapplies a potential difference V_(GS) between the gate and the source ofthe transistor T2, which is equal to the potential difference at theterminals of the drain-source junction of the transistor M2, whichpotential difference is inversely proportional to the input voltage VDD.Since the potential difference between the input voltage VDD and the tapP has a small value, the potential difference V_(GS) has a value whichis sufficiently high to render the transistor T2 equivalent to a closedswitch.

In other words, when such a control circuit controls a transistor of theN-MOS type equivalent to a closed switch, it provides the possibility ofapplying a potential V_(G) to the gate of the transistor T2 which isslightly smaller than the input voltage VDD by a quantity E (of aboutseveral volts) so as to get rid of fluctuations of the input voltageVDD, in contrast to the prior-art converter in which a potential whichis equal to VDD would be applied to the gate of the transistor T2.

FIG. 5 shows a device SCR for reading smart cards, comprising a voltageconverter CONV according to the invention.

The device SCR comprises an input voltage source VDD connected to theinput of a voltage converter according to the invention, as describedwith reference to FIG. 2. The converter CONV provides the possibility ofsupplying an output voltage Vout having a stronger amplitude than theinput voltage VDD. Based on this output voltage Vout, a set of outputvoltages is generated by means of a voltage regulator REG, in which theregulation of these output voltages is effected on the basis of areference voltage Vref within the reading device SCR. Particularly,these output voltages have a level of 5 volts, 3 volts and 1.8 volts andare intended to feed a smart card SM communicating with the device SCRfor the purpose of exchanging data DAT.

The voltage converter according to the invention can be advantageouslyintegrated in an integrated circuit, particularly an integrated circuitdedicated to the management of a device for reading smart cards.

1. A voltage converter for generating an output voltage at an outputterminal from an input voltage taken from ground, said voltage convertercomprising: a capacitance having a first terminal and a second terminal,four transistors of the type functioning as switches, each transistorbeing controlled by a control signal having a level varying in therhythm of a clock signal, each transistor comprising a source, a gate, adrain, and such that the first transistor is connected between the inputvoltage and the first terminal, the second transistor is connectedbetween the first terminal and ground, the third transistor is connectedbetween the input voltage and the second terminal, and the fourthtransistor is connected between the second terminal and the outputterminal, characterized in that it comprises at least a control circuitfor supplying said control signal applied between the gate and thesource of one of the transistors functioning as a switch, said controlcircuit having the particular function of generating a control signalhaving an amplitude which is inversely proportional to the input voltagewhen the transistor which it controls is equivalent to a closed switch.2. A voltage converter as claimed in claim 1, characterized in that saidcontrol circuit comprises, when it controls a transistor of the P-MOStype: an additional tansistor of the P-MOS type functioning as a closedswitch, a current source arranged in series with the drain-sourcejunction of said additional transistor, a switch having two inputs, thefirst input of which is connected to the central tap of the additionaltransistor and the current source, and the second input is connected tothe input voltage, said switch being controlled via said clock signal.3. A voltage converter as claimed in claim 1, characterized in that saidcontrol circuit comprises, when it controls a transistor of the N-MOStype: an additional transistor of the N-MOS type functioning as a closedswitch, a current source arranged in series with the drain-sourcejunction of said additional transistor, a switch having two inputs, thefirst input of which is connected to the central tap of the additionaltransistor and the current source, and the second input is connected toground, said switch being controlled via said clock signal.
 4. Anintegrated circuit comprising a voltage converter for generating anoutput voltage at an output terminal from an input voltage taken fromground, said voltage converter comprising: a capacitance having a firstterminal and a second terminal, four transistors of the MOS typefunctioning as switches, each transistor being controlled by a controlsignal having a level varying in the rhythm of a clock signal, eachtransistor comprising a source, a gate, a drain, and such that the firsttransistor is connected between the input voltage and the firstterminal, the second transistor is connected between the first terminaland ground, the third transistor is connected between the input voltageand the second terminal, and the fourth transistor is connected betweenthe second terminal and the output terminal, characterized in that thevoltage converter comprises at least a control circuit for supplyingsaid control signal applied between the gate and the source of one ofthe transistors functioning as a switch, said control signal having theparticular function of generating a control signal having an amplitudewhich is inversely proportional to the input voltage when the transistorwhich it controls is equivalent to a closed switch.
 5. A device forreading smart cards, comprising a voltage converter for generating anoutput voltage at an output terminal from an input voltage taken fromground, said voltage converter comprising: a capacitance having a firstterminal and a second terminal, four transistors of the MOS typefunctioning as switches, each transistor being controlled by a controlsignal having a level varying in the rhythm of a clock signal, eachtransistor comprising a source, a gate, a drain, and such that the firsttransistor is connected between the input voltage and the firstterminal, the second transistor is connected between the first terminaland ground, the third transistor is connected between the input voltageand the second terminal, and the fourth transistor is connected betweenthe second terminal and the output terminal, characterized in that thevoltage converter comprises at least a control circuit for supplyingsaid control signal applied between the gate and the source of one ofthe transistors functioning as a switch, said control signal having theparticular function of generating a control signal with an amplitudewhich is inversely proportional to the input voltage when the transistorwhich it controls is equivalent to a closed switch.